Doubt clarification Session#1:
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DDR memories are organised as channels, each channel can have one or more ranks.Each Rank is group of DDR memories(Xn). Number of DDR memories is decided based on data bus size.Ex: 64 bit data bus, X8, Each rank will have 8 memories.If we are using, 2n pre-fetch architecture, at a high level, DDR's internal data bus is twice the width of the external data bus. It has been done so that, data can be transferred as both the edges of the clocks(Double Data rate).
Each memory is organised in to multiple Banks. For any access, only one Bank is selected. Prefetch will only work on that bank. Ex: If we are accessing 64 bit data, on Dual rank channel.One of the ranks will be selected, each rank will have say 8 memories, each memory has 4 banks.Bank#2 of all 8 memories will be selected. Each bank will provide 16 bits of data on internal bus(as per 2n-prefetch). One set of 64 bit data will be provided on one edge of the clock, next 64 bits on falling edge.