This video shows how to control the frequency of counters on an FPGA using the pulse-per-second (PPS) signal from a GPS receiver. This allows the counter frequency to be very accurate.
The project supports both the Tang Nano 20K and Tang Nano 9K FPGA development boards. The FPGA contains a PicoRV32 soft RISC-V core that runs software that implements a feedback loop that maintains the counter frequency accuracy.
The sensitivity is high enough to show changes in the FPGA oscillator's frequency caused by small changes in temperature.
Chapters
0:00 Introduction
0:56 Counter design
1:49 Registers
2:16 Clock domains
2:30 Feedback loop
3:05 Setup
3:16 Convergence demo
7:08 Alignment demo
8:07 Software
11:09 Stability
12:00 Temperature
13:16 Summary
Previous video: https://youtu.be/IIL5N2uNmXY gives details on the counter design.
Video on clock domains: https://youtu.be/120bPwaeFKE
Project github:
https://github.com/grughuhler/picorv32_tang_nano_unified
To get the project:
git clone https://github.com/grughuhler/picorv32_tang_nano_unified.git
(if anyone knows how to stop YouTube from converting the text in the line above into a link, please let me know in the comments!)
and then checkout a tag. The first form checks out in a detached head state. This is OK if you don't plan to use git to track changes. The second form checks out the tag on a new local branch.
git checkout pps_gps
git checkout -b name_you_pick pps_gps
Then first build the software for the 9k or the 20k, for example:
cd c_code; make clean; make 20k
and then use the Gowin project file for the 9k or the 20k to build the Verilog bitfile.
See READMEs, the software Makefile, and videos on the PicoRV32 Mini SoC playlist for more information including how to acquire build tools. In particular see 4:10 on https://youtu.be/I-N0brdlzzk for how to set clock 0 to 27MHz on the Tang Nano 20K. The project assumes a 27 MHz clk_in.
The PicoRV32 core is from: https://github.com/YosysHQ/picorv32