Metrics Driven Sign-Off for SoC Specific Logic (SSL) Using Formal Techniques

Presented at DVCon U.S. 2021 IPs/SS are generally pre-verified in a standalone environment, but SoC specific logic (SSL) is tailor made for each SoC. Formal verification comes in handy to provide early feedback on these SSL, to assist the overall theme of “Shift Left” in verification. While formal has now gained a lot of traction for its bug hunting applications, verification engineers are still not fully aware that using formal, it is even possible to fully sign-off portions of the SoC design (SSL in context of this paper). This paper discusses a comprehensive novel technique using formal techniques to: (a) Fully sign-off standalone verification of SSL. (b) Assist simulation in overall coverage closure of these SSL. In addition, this paper also discusses maintenance of formal setups across design releases: (a) Formal Regression Setup (b) Formal Verification Weekly Metrics generation (c) Automated Formal Coverage Collection & Reporting. By: Abhinav Gaur, NXP Semiconductors Gaurav Jain, NXP Semiconductors Ruchi Singh, NXP Semiconductors https://dvcon.org https://dvcon-proceedings.org