PolarFire® FPGA & PolarFire® SOC DDR PHY Initialization and Training Sequence for DRAM Interfaces

Microchip’s DDR-PHY is an integral part of the PolarFIre® FPGA and Polarfire® SOC memory subsystem. This video covers the steps the DDR-PHY sequences through in order to bring up the memory interface for DDR3, LPDDR3, DDR4 and LPDDR4.