Improving performance in AI designs involves the usual tradeoffs in power and performance, but achieving a good balance is becoming much more challenging. There is more data to process, new heterogeneous architectures to contend with, and much higher utilization rates. Andy Nightingale, vice president of product management and marketing at Arteris, talks with Semiconductor Engineering about where the bottlenecks are, how to minimize them in data-intensive workloads across a variety of vertical markets, and why networks on chip are essential to moving and managing this data and getting chips to market on time.