Writing UVM/SystemVerilog Testbenches for Analog/Mixed-Signal Verification

This webinar focuses on how to write UVM testbenches for analog/mixed-signal circuits. UVM (Universal Verification Methodology) is a framework of standardized SystemVerilog classes to build reusable and scalable testbenches for digital designs, and it can be extended to verifying analog circuits simply by using a fixture module that generates analog stimuli and measures analog responses with Scientific Analog’s XMODEL. - Webinar Page: https://www.scianalog.com/webinars/w20220621 - Scientific Analog Website: https://www.scianalog.com/ - Email: [email protected]